(a) Technical Field
The present invention relates to a method for forming a metal interconnection of a semiconductor device, and more particularly to a method for forming a via hole and a trench for a dual damascene interconnection.
(b) Description of Related Art
The introduction of a copper interconnection having an electrical characteristic superior to aluminum (Al) or tungsten (W) has resulted in the use of a dual damascene process for overcoming the difficulty in dry etching copper. In the dual damascene process, a via hole and a trench are first formed, the via hole and the trench are filled with a copper film, and then a planarization process is performed.
FIGS. 1A and 1B are sectional views illustrating a method for forming a via hole and a trench for a conventional dual damascene interconnection. FIGS. 2 and 3 are sectional views illustrating problems of the method illustrated in FIGS. 1A and 1B.
Referring to FIG. 1A, first, an etch stop film 110 and an inter-metal insulating film 120 are sequentially formed on a lower metal film 100. Subsequently, a via hole 130 is formed by performing an etching process using a mask pattern for via hole formation. Next, a bottom antireflective coating (BARC) film 140 is formed on an entire surface in such a manner that via hole 130 is completely filled with BARC film 140. Then a mask pattern 150 for trench formation is formed on BARC film 140.
Next, as shown in FIG. 1B, exposed portions of BRAC film 140 and inter-metal insulating film 120 are etched up to a certain depth to form a trench 170 by performing an etching process using mask pattern 150 for trench formation as an etch mask.
As shown in FIG. 2, however, BARC film 140 has poor flatness due to via hole 130, which may result in misalignment in a subsequent photolithography process. In addition, a void 160 may be generated within via hole 130. In this case, the etching process for forming trench 170 can generate a fence, as denoted by reference numeral “a.”
FIG. 4 is a flow chart illustrating an example of a method for forming a via hole and a trench for another conventional dual damascene interconnection for overcoming the above problem. FIGS. 5 to 7 are sectional views illustrating steps in FIG. 4.
Referring to FIGS. 4 and 5, after an etch stop film 210 and an inter-metal insulating film 220 are sequentially formed on a lower metal film 200, a via hole 230 is formed in inter-metal insulating film 220, exposing a portion of a surface of etch stop film 210. (Step 410.) Next, a photoresist film 240 is formed on an entire surface and filled in via hole 130 (Step 420). Next, as shown in FIG. 6, a recess process for photoresist film 240 is performed. (Step 430.)
Subsequently, as shown in FIG. 7, after a back side cleaning process is performed (Step 440), a BARC film 250 is formed on an entire surface (Step 450). In addition, a mask pattern 260 for trench formation is formed on BARC film 250 (Step 460).
Thereafter, at Steps 470 and 480, a trench is formed by performing an etching process using mask pattern 260. Mask pattern 260 for trench formation and BARC film 250 are sequentially removed, as is photoresist film 240 within via hole 230. In addition, the portion of etch stop film 210 exposed through via hole 230 is removed to form a via hole and a trench for a dual damascene interconnection.
A problem with the method described above in FIGS. 4-7 is that semiconductor device fabrication apparatuses must be used alternately in order to perform the above conventional method. More specifically, Steps 410 and 420 must be performed in a photography apparatus, Step 430 must be performed in an asher apparatus, Step 440 must be performed in a cleaning chamber, and Steps 470 and 480 must be performed in the photography apparatus again.
Accordingly, the conventional method has poor efficiency due to a long process time. Particularly, surface roughness in the ashing process is increased and there are detects due to remaining polymer.